(1) Field of the Invention
The present invention relates to a method for making a semiconductor device in a silicon semiconductor well surrounded by an insulating layer by means of silicon-on-insulator techniques.
(2) Description of the Prior Art
Active parasitic devices, such as, parasitic metal oxide semiconductor transistors or parasitic bipolar transistors are formed in PN junction separation structures that appear in complementary metal oxide semiconductor devices. In addition, there are problems of deterioration of electric devices and soft error the known latch-up phenomenon. In order to prevent these problems and attain high density, silicon-on-insulator (SOI) techniques have been studied having insulating layers formed as sidewalls of an insulating substrate the sidewalls are formed of a material such as SiO.sub.2 and silicon single crystalline wells are formed in these insulating layers to form semiconductor devices in the wells.
These techniques have the advantage of perfect isolation of electrical elements, high speed performance, latch-up free operation and being soft error free. A semiconductor device such as CMOS circuits, can be made using these techniques. Second, the width of the insulating layers for isolation depends only on photo-etching, etc. Third, high integration based on the micro-miniaturization can be obtained as well as the application with three-dimensional devices. According to the above techniques, a semiconductor device having an SOI structure is formed by forming an amorphous or polysilicon layer on an amorphous insulating substrate such as SiO.sub.2 and performing recrystallization on the polysilicon layer. Separation by implanted oxygen (SIMOX) processes, full isolation by phorous oxidized silicon (FIPOS) processes, or zone melting recrystallization (ZMR) are also known as another approach.
Recently, SOI MOSFETs have been formed on a ultra-thin film of less than 1000 angstroms have been obtained having the effect of removing the kink and improvement of the sub-threshold characteristic curve.
In addition to this, a study has been made of the manufacture of the SOI Gate-All-Around MOSFET structure. When a lower part of a hook-shape gate is formed underneath an active silicon region, in order to form an SOI wafer, the channel length of the lower part is dependent on the channel width region being larger than the lower part of the channel width by isotropic wet etching, and the thickness of a buried oxide layer is more than half of the lower part of the channel width region. Accordingly, there is a limit to increasing the channel width region. If the thickness of the buried oxide layer of the SOI wafer is increased, energy and dose of oxygen ion implantation is remarkably increased, and defects are generated in the active silicon region to degrade the electrical characteristics.
In accordance with the present invention, there are made a perfect separation implanted oxygen (SIMOX) wafer and a partial separation implanted nitrogen (SIMNI) wafer, and by forming a buried oxide layer and an oxynitride layer included in the buried oxide layer and partially buried and making devices by selective etching, a channel length region is formed to be independent to a channel width or a thickness of the buried oxide layer.